1. Field of the Invention
The present invention relates generally to computer processors with level-two caches, and more particularly to methods and structures for using the level-two cache for rollback when a plurality of processor cores is running in lockstep.
2. Description of Related Art
In a prior art system 100, high reliability was attempted by running processor 110 and processor 120 in lockstep. However, while conceptually this was straightforward, in practice it was difficult to implement.
System 100 had an external clock 160 and each processor 110, 120 had its own internal clock. To assure that processors 110, 120 were operating in lockstep, it was necessary to monitor stores to level-two caches 130, 140 for example by a lockstep monitor 150. For example, if different values were stored at a given point in time, processors 110, 120 were not in lockstep, or an error had occurred in one of both of processors 110, 120.
Assuring that the various clocks were synchronized and operating on the same cycle was a difficult problem. If the internal clocks diverted from the external clock, system 100 could not function reliably, because it was not possible to verify that the data was associated with the same processor clock cycle for example. New techniques are needed for verifying that processors operate in lockstep in a high reliability system.